Application of a Digital Test Core to a Test Bed for Bit-Parallel Optoelectronic Communications

A programmable FPGA-based digital logic circuit is enhanced with high-speed emitter-couple logic and optoelectronics laser drivers and receivers to create a testbed for evaluating methods of transferring parallel data words in sub-nanosecond bursts. The end application requires the transfer of entire address/data buss information within a single cycle of the computer processor, which is running at several gigahertz. In this paper, the programmable logic core is used to form a lowcost, yet very precise and flexible instrument for emulating the buss activity, converting the data to bitparallel format, transmitting optically, and capturing the received data. The testbed has been built to demonstrate complete end-to-end operation of a 4-bit parallel slice of the communication channel. Bit periods shorter than 300ps and timing precision of about 20ps is demonstrated.